The present invention relates to a semiconductor memory device, and more particularly to a substrate bias generator which makes device characteristics stable by supplying a predetermined negative voltage to a substrate and minimally reduces current consumption during a self refresh mode.
In general, a P-type substrate is employed in a dynamic RAM having a memory cell which is composed of one access transistor and one storage capacitor. Further, it is well known that a substrate bias generator must be included in the use of the P-type substrate, the substrate bias generator supplying a negative voltage of a predetermined level to the substrate. In the meantime, the substrate bias generator is installed in inside of a chip and the negative voltage is thus provided to the substrate because there are the following some advantages, compared with a case of connecting the substrate to a ground terminal GND. First, it is possible to minimize variation of a threshold voltage generated by body effect of a transistor and it is possible to obtain efficiency of operational speed by making a punch-through voltage high and by reducing a junction capacitance. Second, in order to protect the memory device, it is possible to suppress forward-bias by reducing sub-threshold current and by undershooting an input voltage of TTL(Transistor-Transistor Logic) input stage. According to the above advantages, if the constant negative voltage is provided to the substrate by the substrate voltage generator, the function of the memory device is generally improved.
In the meantime, the substrate bias generator of which driving capacity is improved is disclosed in U.S. Pat. No. 5,157,278 entitled “Substrate Voltage Generator for Semiconductor Device” granted on 20 Oct. 1992. FIG. 1 is a schematic block view showing a substrate bias generator disclosed in the above U.S. Pat. No. 5,157,278. FIG. 1 is composed of a voltage pump circuit 6 providing a substrate voltage VBB, a substrate voltage level detector 10 detecting the voltage level of the substrate voltage VBB, a signal delay circuit 2 delaying an output signal of the substrate voltage level detector 10 during a predetermined time and thereby generating the output signal, and an oscillator 4 performing an oscillating operation in response to the output signal of the signal delay circuit 2 and driving the voltage pump circuit 6. In such a construction, if the oscillator 4 is operated, the substrate voltage VBB is synchronized with an oscillating signal φOSC generated in the oscillator 4 and is boosted to a predetermined negative voltage by the voltage pumping operation of the voltage pump circuit 6. In the meantime, the substrate voltage level detector 10 shown in a dotted line block, includes a PMOS transistor 12 having a channel formed between a power supply terminal Vcc and a connecting node 14 and being always apt to be turned on, a PMOS transistor 16 whose source terminal is connected to the connecting node 14 and whose gate terminal is connected to the substrate voltage VBB, an NMOS transistor 18 having the channel formed between the PMOS transistor 16 and a ground terminal Vss and being always apt to be turned on, and an inverter 20 having an input terminal coupled to the connecting node 14 and driving the signal delay circuit 2. The substrate voltage level detector 10 detects the level of the substrate voltage VBB and controls the oscillator 4 in response to such a detecting operation. Therefore, in case that the voltage level of the substrate voltage VBB is over a desired negative voltage level (in this case, an absolute value of the substrate voltage VBB is small), the substrate voltage VBB is boosted to the desired negative voltage level by generating a signal to enable the oscillator 4 and by operating the oscillator 4. On the other hand, in case that the voltage level of the substrate voltage VBB is below the desired negative voltage level (in this case, the absolute value of the substrate voltage VBB is large), the substrate voltage VBB is continuously maintained at the desired negative voltage level by generating the signal to enable the oscillator 4 and by stopping the operation of the oscillator 4. The signal delay circuit 2 receiving the output signal of the substrate voltage level detector 10, prevents the voltage level of the substrate voltage VBB being sensitively varied and thereby makes the operation of the substrate bias generator stable.
In the construction of the substrate voltage level detector 10 detecting the voltage level of the substrate voltage VBB, the PMOS transistor 16 is switch-controlled by the substrate voltage VBB according to a gate-input of the substrate voltage VBB. Accordingly, if the voltage level of the substrate voltage VBB becomes high, the voltage level charged to the connecting node 14 is raised. The inverter 20 is output at the “low” level. In this case, the oscillator 4 is enabled. On the other hand, if the voltage level of the substrate voltage VBB becomes low, the voltage level charged to the connecting node 14 is dropped. The inverter 20 is output at the “high” level. In this case, the oscillator 4 is disabled. The substrate voltage VBB softly or heavily turns on the channel of the PMOS transistor 16, however, it can completely not turn off the channel thereof. Therefore, the PMOS transistors 12 and 14 and the NMOS transistor 18 are always turned-on, so that direct current flows between the power supply terminal Vcc and the ground terminal Vss. Further, the voltage level charged to the connecting node 14 is set near a trip point of the inverter 20, so that the other direct current flows between the power supply terminal Vcc and the ground terminal Vss in the inverter 20(this is generally composed of a CMOS inverter). Therefore, the current of the substrate voltage level detector 10 always flows in case of powering-up of the chip regardless of the operation of the semiconductor memory device. This specially causes the consumption of the operational current to be increased during a stand-by state.
In the meantime, in case of the cell which has the dynamic construction such a dynamic RAM, it is well known that a refresh mode is included as one operational mode in the semiconductor memory device so as to perform a rewrite operation of cell storage data. In special, a self refresh mode is generally employed in the semiconductor memory device, the self refresh mode performing a refresh operation according to an interval of constant time. The dynamic RAM performing low current consumption during the self refresh mode, is disclosed in pages 43 to 44 of a paper from “1993 Symposium on VLSI circuits, entitled “Low power Self Refresh Mode With Temperature Detecting Circuit”. As well known, the self refresh mode is divided into active and stand-by states. The active and stand-by states of the self refresh mode have a constant interval, respectively. The interval is determined in the design of the chip. Accordingly, it is well known that the stand-by state of the self refresh mode is generated at a constant interval unlike that of the chip, and that the stand-by state thereof is longer maintained than the active state thereof (actually, the stand-by state occupies most self refresh mode). This is well known from the above paper or from data books of Samsung Co., Ltd. published 1992 and 1993. As mentioned above, during the stand-by state of the self refresh mode, the direct current flows into the ground terminal Vss from the power supply terminal Vcc in the substrate voltage level detector 10, thereby generating the current consumption. On the other hand, in case that the time when the semiconductor memory device is stayed in the stand-by state is similar to or is shorter than the operational period of the substrate bias generator, during the stand-by state, the substrate bias generator doesn't need to operate, however, only during the active state, it should operate. Thereby, the current consumption according to the substrate voltage is prevented from being increased during the stand-by state. However, since time of the stand-by state is not determined in the operation of the general semiconductor memory device, it is impossible to reduce the current consumption under the stand-by state according to the above method. In the self refresh mode to be refreshed by the period of the chip, since the time when the semiconductor memory device is stayed in the stand-by state and the active state is determined by the period generated in inside of the chip, it is possible to know the time when the semiconductor memory device is stayed in the stand-by state. Nevertheless, the current consumption generated in the chip is in total increased according to the current consumption generated from the substrate voltage level detector 10 during the stand-by state of the self refresh mode. It has been estimated that such increase of the current consumption can interfere with the suppression of the power consumption in the superhigh integrated semiconductor memory device having low power.